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| em78p 447n otp rom em78p447n 8-bit micro-controller version 1.0
em78p 447n otp rom specification revision history version content 1 . 0 i n i t i a l versio n 29/10/20 0 4 application note an-0 01: sev e n-s e gmen t and i/o port an-0 02: ke y s tro ke time s displa y e d b y se v e n-segment an-0 03: j u mping out of delay subr outine loop b y external ke y s troke an -0 04: le d w i th con t rol l ed rot a ting direc t ion an-0 05: sin g a song "dr a w " of em78 447 an-0 06: ste pping motor an-0 07: em7 8 p447s v . s. em78p44 7 on the dc cha r acteristic s and progr am timing an-0 08: abo u t em78p4 4 7 s sleep2 mode se tting this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 2 em78p 447n otp rom 1. general description em78p44 7n is an 8-bit mi croprocesso r with low-po wer and hig h -speed cmos techn o logy a nd high noise immunit y . it is equi pped with 4k* 13-bits elect r i c al on e time prog ramm abl e rea d only memo r y (otp-ro m ). it provides three prote c t i on bits to prevent use r ?s code in the ot p memory fro m being intrud ed. seven option b i ts are al so a v ailable to m eet use r ? s req u irem ents. with its otp - rom featu r e, the em78 p447 n is abl e to offer a conve n ient way of develo p ing a nd verifying u s er?s p r og ram s . more over, u s er can ta ke a d vantage of elan writer to easily p r o g r am hi s develop ment cod e . this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 3 em78p 447n otp rom 2. features ? operatin g voltage rang e: 2.5v~5.5v. ? operatin g temperature ra nge: -4 0 em78p 447n otp rom ? 99.9% singl e instructio n cycle comm a nds ? the transi e nt point of system freq uen cy betwe en hxt and lxt is aroun d 400 khz this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 5 em78p 447n otp rom 3. pin assignment tcc vd d nc vs s /int p50 p51 p53 p60 p61 p62 p63 p64 p52 /reset os c i os c o p7 7 p7 6 p7 5 p7 4 p7 2 p7 1 p7 0 p6 7 p6 6 p6 5 p7 3 em 78p4 47n ap em 78p 447n a m 1 2 3 4 5 6 7 8 9 10 11 12 14 13 26 25 24 23 22 21 20 19 18 17 16 15 27 28 di p sop tc c vd d vs s /i n t p5 0 p5 1 p5 3 p6 0 p6 1 p6 2 p6 3 p6 4 p5 2 /r e s et osc i os c o p7 7 p7 6 p7 5 p7 4 p7 2 p7 1 p7 0 p6 7 p6 6 p6 5 p7 3 e m 7 8 p 447 nas 1 2 3 4 5 6 7 8 9 10 11 12 14 13 26 25 24 23 22 21 20 19 18 17 16 15 27 28 vs s ss o p tc c vdd nc vss /in t p5 0 p5 1 p5 3 p6 0 p6 1 p6 2 p6 3 p6 4 p5 2 /rese t osci osc o p7 7 p7 6 p7 5 p7 4 p7 2 p7 1 p7 0 p6 7 p6 6 p6 5 p7 3 em 78p44 7nbp em 78p 447n bwm 1 2 3 4 5 6 7 8 9 10 11 12 14 13 26 25 24 23 22 21 20 19 18 17 29 30 27 28 p5 5 p5 4 p5 6 p5 7 15 16 31 32 di p sop em78p 447n otp rom /int 5 i * external interrupt pin trig gered by falling edg e. v s s 4 - * g r o u n d . nc 3 - * no conn ecti on. t a ble 2 em7 8 p447 nas pin descrip tio n symbol pin no. type fun c tion vdd 3 - * powe r su pp ly . o s c i 2 7 i * xtal type: cry s tal input termin al or ext e rn al clo c k in put pin. * rc type: rc oscillator input pin. o s c o 2 6 i / o * xtal type: output terminal for c r ys tal oscill ator or extern al clock in put pin. * rc type: instru ction clo c k output. * external clo ck sign al inpu t. t c c 2 i * the re al time clo ck/ cou n ter (with sch m itt trigger inp u t pin) mu st be tied to vdd or vss if not in us e. / r e s e t 2 8 i * input pin with schmitt trigger. if this pi n remain s at lo gic low, the controll er will also rem a in in reset condition. p50~p5 3 5~8 i/o * p50~p5 3 are bi-di r e c tion al i/o pins. p60~p6 7 9~1 3 , 15~17 i/o * p60~p6 7 are bi-di r e c tion al i/o pins. these ca n be pulled -hig h intern ally by softwa r e control. p70~p7 7 1 8 ~ 2 5 i / o * p70~p7 7 are bi-di r e c tion al i/o pins. * p74~p7 5 can be pull ed -high inte rnall y by software control. * p76~p7 7 can have op en -drain outp u t by softwa r e control. * p70 and p7 1 can al so b e defined a s the r-option pi ns. /int 4 i * external interrupt pin trig gered by falling edg e. v s s 1 , 1 4 - * g r o u n d . t a ble 3 em7 8 p447 nbp and em78p44 7nbwm pin des c ription symbol pin no. type fun c tion vdd 4 - * powe r su pp ly . o s c i 2 9 i * xtal type: cry s tal input termin al or ext e rn al clo c k in put pin. * rc type: rc oscillator input pin. o s c o 2 8 i / o * xtal type: output termin al for cry s tal oscillato r or e x ternal cl ock i nput pin. * rc type: instru ction clo c k output. * external clo ck sign al inpu t. t c c 3 i * the re al time clo ck/ cou n ter (with schm itt trigger inpu t pin), must b e tied to vdd or vs s if not in use. / r e s e t 3 0 i * input pin wit h schmitt trig ger. if this pi n remai n s at logic lo w, the controll er will keep in reset condition. p50~p5 7 8~ 11,2~1, 32~31 i/o * p50~p5 7 are bi-di r e c tion al i/o pins. p60~p6 7 1 2 ~ 1 9 i / o * p60~p6 7 are bi-di r e c tion al i/o pins. t hese can be pulled -hig h i n tern ally by softwa r e control. p70~p7 7 2 0 ~ 2 7 i / o * p70~p7 7 are bi-di r e c tion al i/o pins. * p74~p7 5 can be pull e d - high inte rnall y by software control. * p76~p7 7 can have op en -drain outp u t by softwa r e control. * p70 and p7 1 can al so b e defined a s the r-option pi ns. /int 7 i * external interrupt pin trig gered by falling edg e. v s s 6 - * g r o u n d . nc 5 - * no conn ecti on. this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 7 em78p 447n otp rom 4. function description io c 5 r5 p 5 0 p 5 1 p 5 2 p 5 3 p 5 4 p 5 5 p 5 6 p 5 7 io c 6 r6 io c 7 r7 acc r3 st ack 1 st ack 2 st ack 3 st ack 4 st ack 5 p c ro m i n st r u ct i o n re g i s t e r i n st r u ct i o n de c o d e r al u in te rr u p t co n t r o l r4 ra m w d t ti m e r pr e s c a l e r o s c illa t o r / t i m i n g co n t r o l wd t ti m e -o u t r1 ( t cc) sl e e p & wa k e co n t r o l da t a & c o nt r o l b u s /in t tc c os c i os c o / r e set p 6 0 p 6 1 p 6 2 p 6 3 p 6 4 p 6 5 p 6 6 p 6 7 p 7 0 p 7 1 p 7 2 p 7 3 p 7 4 p 7 5 p 7 6 p 7 7 fig. 2 functional block diagram 4.1 operational registers 1. r0 (indirect addressing register) r0 is not a physically imple m ented re gist er. its major functio n is to a c t as an indire ct addre s sing pointe r . any instru ctio n usin g r0 as a pointer act ually acce sse s data p o inte d by the ra m select re gister (r4). 2. r1 (time clock /counter) ? increa sed b y an external sign al edge, whi c h is def in ed by te bit (co n t-4) thro ugh the tcc pin, or by t he inst ru c t ion cy cle clo ck. ? writable a n d rea dabl e as any other re giste r s. ? defined by resetting pab (cont - 3). ? the pres caler is ass i gned to tcc, if the pab bit (cont-3) is reset. this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 8 em78p 447n otp rom ? the contents of the prescaler counter will be cl ea red only when tcc regi ster is written a value. 3. r2 (program counter) & sta ck ? depen ding on the devi c e type, r2 and hard w a r e sta ck a r e 1 0 -bit wide. th e structu r e is d epi cted in fig.3. ? generating 1024 u 13 bit s on -chip ot p rom ad dresse s to the relative prog rammi ng in stru ction cod e s. on e p r og ram p age is 102 4 wo rd s long. ? r2 is set a s all "0"s wh en unde r rese t con d ition. ? "jmp" instru ction all o ws d i re ct loadi ng of the lowe r 1 0 program co unter bits. th us, "jmp" all o ws p c to go to any locatio n within a page. ? "call" instruction loa d s t he lowe r 10 b i ts of t he pc, and then pc+1 is pushed in to the stack. thu s , the sub r o u tin e entry add re ss can b e located anywhe r e within a pa ge. ? "ret" ("retl k", "reti") instructio n load s the pr o g ram cou n ter with the cont ents of the top-level st ac k. ? "add r2,a" allows th e co ntents of ?a? t o be a d d ed to the cu rrent p c , and t he ni nth and t enth bits of the pc are cl eared. ? "mov r2,a" allows to lo ad an add re ss from th e "a" regi ster to t he lo we r 8 bit s of the p c , and the ninth and tent h bits of the pc are cle a re d . ? any instructi on that writes to r2 (e .g. "add r2,a", "mov r2,a", "bc r2,6", ? ? ? ? ? ) will cause the ninth and tenth bits (a8~a9) of the pc to be cleared. thus, the compute d jump is limited to the first 256 locatio n s of a page. ? all instru ction are si ngle instru ct ion cycle (fcl k/2 or fclk/4) ex ce pt for the instructio n that woul d cha nge the contents of r2 . such instruct ion will nee d one mo re in stru ction cy cle. a 7 ~ a0 o n -ch i p p r ogr am me m o r y ??? ? ? ??? ? ha rd w a r e v e c t or u s er memor y sp a c e so f t w a r e ve c t o r r e se t v e cto r ? ??? a9 a8 a1 1 a1 0 st ac k le vel 1 st a c k le vel 3 st a c k le vel 2 st a c k le vel 4 st a c k le vel 5 call 00 pa g e 0 00 00 ~03ff 01 pa g e 1 04 00 ~07ff 10 p a g e 2 0 8 0 0 ~ 0b f f 11 p a g e 3 0c 00 ~0 f f f r3 re t re t l re t i fig. 3 program coun ter organi zation this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 9 em78p 447n otp rom aaddr ess r p a g e register s i o c pa g e r egisters 00 r0 (indir ect addr essing r e gister) r eserv e 01 r1 (t ime clock c o unter ) cont (c ontr ol r egister) 02 r2 (p rogra m co unter) r eserv e 03 r3 (s tatus r e gister) r eserv e 04 r4 (r am s e lect r egister) r eserv e 05 r5 (p ort5) io c 5 (i /o port control r egister) 06 r6 (p ort6) io c 6 (i /o port control r egister) 07 r7 (p ort7) io c 7 (i /o port control r egister) 0 8 g e neral r e gister r e serv e 0 9 g e neral r e gister r e serv e 0a g e neral r e gister r e serv e 0b g e neral r e gister io cb (w ake - up c ontr o l re gis t er for p o rt6 ) 0c g e neral r e gister r e v e rse 0d g e neral r e gister r e v e rse 0e g e neral r e gister io c e (w d t ,s lee p 2 ,o pen d r ain,r - o p tion c ontro l register ) 0f g e neral r e gister io c f (i nterrup t m a sk r egister) 10 U em78p 447n otp rom 4. r3 (status register) 7 6 5 4 3 2 1 0 g p p s 1 p s 0 t p z d c c ? bit 7 (gp) gene ral read/ write bit. ? bits 6 (ps1 ) ~ 5 (ps0 ) p age sele ct bit s . ps1~ps0 are u s e d to p r e-sele ct a p r o g ram m e mo ry page . whe n exe c ut ing a "jmp", "call", or other in st ruct ions whi c h causes th e program count er to cha nge (e.g. mov r2, a), ps1~ps0 a r e load ed into t he 11t h an d 12th bit s of th e prog ram co unter and sel e ct one of the available pr og ram memory pag es. note that ret (retl, reti) instru ction doe s not cha nge the ps0 ~ps1 bits. t h at is, the retu rn will al ways be to the p a ge from wh ere the sub r o u tine was called, reg a rdl e ss of the ps1~ps0 bits cu rrent setti ng. ps1 ps0 prog ram me mory pag e [address] 0 0 page 0 [000 -3ff] 0 1 page 1 [400 -7ff] 1 0 page 2 [800 -bff] 1 1 page 3 [c0 0 -fff] ? bit 4 (t) time-o ut bit. set to 1 with the "slep" and "wdt c" co mmand s, or duri ng po we r up, and res e t to 0 with the wdt time-out. ? bit 3 (p) powe r do wn bit. set to 1 during po we r on or by a "wdt c" com m an d and reset to 0 by a "slep" command. ? bit 2 (z) zero flag. set to "1" if the res u lt of an arithmetic or lo gic o peration is ze ro. ? bit 1 (d c) a u xiliary carry flag. ? bit 0 (c ) carry flag 5. r4 (ram select r e gister) ? b i t s 7~6 de termine whi c h ban k is a c tivated amon g the 4 ban ks. ? b i t s 5~0 are use d to sel e ct the re gist ers (ad d re ss: 00~3f) in the indire ct add ressing m ode. ? if no indire ct addressin g is use d , the rsr ca n be used a s an 8-bit gen eral-purpo se re ad /writer regi ster. ? see the con f iguratio n of the data mem o ry in fig. 4. 6. r5~r7 (port 5 ~ p o rt7) ? r5, r6 and r7 a r e i/o re giste r s 7. r8~r1f and r20~r3e (general purpose register) ? r8~r1f, an d r20 ~ r3e (i nclu ding ba n ks 0 ~ 3 ) are g ene ral-pu rpo s e regi sters. this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 11 em78p 447n otp rom 8. r3f (interrupt status register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - e x i f - - t c i f ? bit 3 (exif) external interru pt flag. set by falling edge on /int pi n, flag clea re d by softwa r e ? bit 0 (tcif ) the tcc ove r flow inte rrupt flag. set as tcc overflo w s; flag clea re d by softwa r e . ? bits 1, 2, 4~7 a r e not u s ed and rea d are a s ?0 ?. ? "1" means i n terrupt re qu est, "0" mean s non -inte r ru pt. ? r3f ca n be clea re d by instru ction, but can not be set by instru ctio n. ? iocf is the interrupt mask regis t er. ? note that re ading r3f wil l obtain the re sult of the r3 f "logic and" and iocf. 4.2 special purpose registers 1. a (accumulator) ? internal dat a tran sfer, or instructio n op era nd hol ding . ? it cannot be add re ssed. 2. cont (control register) 7 6 5 4 3 2 1 0 / p h e n / i n t t s t e p a b p s r 2 p s r 1 p s r 0 ? bit 7 (/phen) control bit used to en ab le the pull-hig h of p60~p67 , p74 and p75 pins 0: enable inte rnal p u ll-hi gh. 1: disa ble int e rn al pull-hig h . ? cont regi ster is both rea dable a nd wri t able. ? bit 6 (/int) interru pt ena ble flag 0: masked by disi or hard w a r e interru p t 1: enable d by eni/reti instructio ns ? bit 5 (ts) t cc sign al so urce 0: int e rnal in s t ruct io n cy cl e clo ck 1: transitio n o n tcc pin ? bit 4 (te) t cc sign al ed ge 0: increment i f the transitio n from low to high takes pl ace o n tcc pin 1: increment i f the transitio n from high to low take s pla c e on t c c pi n ? bit 3 (pa b ) prescal e r a ssignme n t bit. this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 12 em78p 447n otp rom 0: tcc 1: wdt ? bit 2 (psr2 ) ~ bit 0 (psr0 ) tcc/wdt pre s cale r bi ts. psr2 psr1 psr0 tc c rate wd t rate 0 0 0 1 : 2 1 : 1 0 0 1 1 : 4 1 : 2 0 1 0 1 : 8 1 : 4 0 1 1 1 : 1 6 1 : 8 1 0 0 1 : 3 2 1 : 1 6 1 0 1 1 : 6 4 1 : 3 2 1 1 0 1 : 1 2 8 1 : 6 4 1 1 1 1 : 2 5 6 1 : 1 2 8 3. ioc5 ~ ioc7 (i/o p o rt control register) ? "1" put the relative i/o pin into high imp edan ce, while "0" defines the rel a tive i/o pin as o u tp ut. ? ioc5 and ioc7 regi sters are both re adabl e and writable. 4. iocb (wake-up control register for port6) 7 6 5 4 3 2 1 0 / w u e 7 / w u e 6 / w u e 5 / w u e 4 / w u e 3 / w u e 2 / w u e 1 / w u e 0 ? bit 7 (/wue 7 ) control bit is used to en able the wake-u p functio n of p67 pin. ? bit 6 (/wue 6 ) control bit is used to en able the wake-u p functio n of p66 pin. ? bit 5 (/wue 5 ) control bit is used to en able the wake-u p functio n of p65 pin. ? bit 4 (/wue 4 ) control bit is used to en able the wake-u p functio n of p64 pin. ? bit 3 (/wue 3 ) control bit is used to en able the wake-u p functio n of p63 pin. ? bit 2 (/wue 2 ) control bit is used to en able the wake-u p functio n of p62 pin. ? bit 1 (/wue 1 ) control bit is used to en able the wake-u p functio n of p61 pin. ? bit 0 (/wue 0 ) control bit is used to en able the wake-u p functio n of p60 pin. 0: enable inte rnal wa ke-up. 1: disa ble int e rn al wa ke -u p. ? iocb regi ster is both rea dable a nd wri t able. 5. ioce ( w dt control register) 7 6 5 4 3 2 1 0 - o d e wd t e s l p c ro c - - / w u e ? bit 6 (ode ) control bit is use d to enabl e the open -d rain of p76 an d p77 pin s 0: disa ble op en-drai n outp u t. this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 13 em78p 447n otp rom 1: enable op en-drai n outp u t. the o d e bit can b e re ad a nd written. ? bit 5 (w dt e) cont rol bit use d to enabl e watchdo g timer. the wdte bi t is useful o n l y when enwdt, the co de option bit, is "0". it is only when th e enwdt bit is "0" that wdte bit. is ab le to disabl ed /enable d the wdt. 0: disa ble wdt. 1: enable wdt. the wdte bi t is not u s ed if enwdt, the co de optio n bit enwdt, i s "1". that i s , if the enwdt bit is "1", wdt is a l ways di sa ble d no ma tter what the wdt e bit status is. the wdte bi t can be read and written. ? bit 4 (slpc ) thi s bit i s set by hardware at the lo w l e vel trigg e r of wa ke -up sig nal an d i s cl e a red b y software. slpc is used t o control t he oscillator operation. t he oscill ator i s di sabled (oscillator is stopped, and the controller enters into sleep2 mode) on the high- to-low transition and is enabled (controll er i s awakened f r om sleep2 mode) on l o w-to -hi gh transiti on. in order t o ensure the stabl e output of the oscillato r, once the oscill ato r is enabl ed a gain, there is a delay for approximately 1 8 ms 1 (o scill ator sta r t-up timer, ost) before the next instruction of the program is executed. the o s t is alway s activa ted by a wake-u p event from sl eep mo de rega rdl e ss of the code option bit enwdt status i s "0" or othe rwi s e. after waki ng up, t he wdt is ena bled if the co de opti on enwdt is "1". the block diagram of sleep2 mode and wake-up invoked by an input trigger is depicted in f i g. 5 . the slpc bit can be rea d and written. ? bit 3 (ro c ) roc i s used for the r-opti on. setting roc to "1" will enabl e the st atus of r-opti on pin s (p70, p71) for the controlle r to read. clearin g roc wil l disable the r-option function. otherwi se, the r-option function is introduc ed. us ers mus t connec t the p71 pin or/and p70 pin to vss with a 430k ? em78p 447n otp rom 6. iocf (interrupt mask register) 7 6 5 4 3 2 1 0 - - - - e x i e - - t c i e ? bit 3 (exie) exif interru pt enable bit. 0: disabl e exif interru pt 1: enable exif interrupt ? bit 0 (tcie) tcif interru p t enable bit. 0: disabl e tcif interru pt 1: enable t c i f interrupt ? bits 1, 2 and 4~7 not used. ? individual interru pt is ena bled by settin g its asso ciat ed co ntrol bit in the iocf to "1". ? global interrupt is enabl e d by the eni instructio n an d is disa bled by the disi in stru ction (refe r to fig . 9). ? iocf reg i ster is bot h readable and writable. osc i llator en a b le d i s a b l e rese t qd q cl k pr cl cl ea r fr o m s / w se t 2 /w u e 0 /w u e 1 /w u e 7 vcc p6 0 ~ p 6 7 vcc /wue p7 4 ~ p 7 5 /phe n 8 fig. 5 sleep mode and w ake -up circ uit s on i/o port s bloc k di agram this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 15 em78p 447n otp rom 4.3 tcc/wdt & prescaler an 8-bit cou n t er is availabl e as prescal e r for the tc c or wdt. t he pre s cale r is a v ailable fo r ei ther the tcc or wdt only at any given time, and the pab bit of the cont regi ster is used to determine the pre s cale r a ssi gnme n t. the psr0~ps r2 bits dete r min e the ratio. th e pre s cale r is clea re d ea ch time the instructio n is written to tcc unde r tcc mode. t he wdt and prescaler, wh en assign ed to wdt mode, are clea red b y the ?wdt c ? or ?slep? in stru ction s . fig. 6 depict s the ci rcuit dia g ram of t cc/ wdt. ? r1 (tcc) is an 8-bit timer/counte r . the clock sou r ce of tcc can b e internal or e x ternal clo ck i npu t (ed ge sele cta b le fro m t cc pin). if tcc si gnal so urce i s from inte rn al clo ck, t c c wi ll increa se by 1 at every instru ction cycle (without pre s cale r). refe rring to fig. 6, clk=fo sc/2 or clk=f o sc/4 sele ction i s d e termin ed by the co de o p tion bit clk status. clk = fosc/2 i s u s e d if clk bit i s "0", and clk=fo sc/4 is u s e d if clk bit is "1". if tcc sig nal sou r ce come s from extern al clo ck i nput, tcc is incre a sed by 1 at every falling edg e o r risi ng ed ge of tcc pi n. ? the watch d og timer is a free runni ng o n -chip rc o s cillato r. the wdt will ke e p on run n ing even afte r the oscillator driver h a s be en turne d off (i.e. in sleep mode ). duri ng norm a l ope rat i on or sl eep m ode, a wdt time-o ut (if enable d ) will cau s e the device to re set. the wdt can b e ena bl ed or di sa ble d any time duri ng n o rmal mod e by softwa r e p r og rammi ng. refe r to wdte bit of ioce regi ster. wi thou t pre s cale r, the wdt time -o ut perio d is a pproximately 18 ms 1 (defaul t). wd t te tc c 8 - b i t c o u n ter 2 cy cles t cc( r 1 ) sync pin m x u m x u m x u 8 -to -1 m u x mux ts 0 ps r 0 ~ p s r 2 w d t tim e u o t pa b t c c o v erflo w in terru p t c l k ( = f os c / 2) pa b (in i o c e ) wd t e da t a bu s pa b 1 0 1 0 1 01 fig. 6 tcc a nd wdt blo ck diagr a m 1 em78p 447n otp rom 4.4 i/o ports the i/o re gisters, port 5, port 6, and port 7, are b i -directio nal t r i-state i/o p o rts. th e fun c tion s of pull-hig h , r-option, an d open -d rain can be pe rfor med inte rnall y by cont and io ce re spe c tively. there is inp u t status chan g e wa ke-up fu nction o n po rt 6, p74, and p75. each i/o pin ca n be defined a s "input" or "o u t put" pin by the i/o co ntro l regi ster (io c 5 ~ ioc7). the i/o re gisters and i/o cont rol regi sters a r e both re ada bl e and writabl e. the i/o interf a c e ci rcuits for port 5, port 6, and port 7 are sho w n in fi g u re s. 7(a ) an d (b) re spe c ti vely. pdr d q q cl k d pc w r pd w r q q cl k d pr cl po r t 0 1 m u x io d pcr d pr cl fig. 7 (a) the i/o port and i/o control register cir c uit p drd q q cl k d pc w r pd w r q q cl k d 0 1 m u x io d ro c vc c we a k l y pull - u p po rt re x* *t he r e x i s 43 0k oh m e x t e rna l res i st o r p crd pr cl pr cl this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 17 fig.7(b) the i/o port w i th r-o p tion (p70, p71) cir c uit em78p 447n otp rom 4.5 reset and wake-up 1. reset a reset is initiated by one of the following events- (1) po we r on re set, or (2) /reset pin input ?low?, or (3) wdt timeout. (if enable d ) the device is kept in a reset conditio n for a period of approx. 18m s 1 (one oscill ator sta r t-up timer period) after the res e t is detec t ed. once the reset oc curs , the following func tions are performed (refer to fig.8). ? the oscillat o r starts or is running ? the program counter (r2) is s e t to all "1". ? when po we r is switched on, bits 5~6 o f r3 and the uppe r 2 bits o f r4 are clea red. ? all i/o port pins a r e confi gured a s inpu t mode (hig h-i m ped an ce st ate). ? the watchd og timer an d pre s cale r are clea re d. ? upon po we r on, the bits 5~6 of r3 a r e clea re d. ? upon po we r on, the uppe r 2 bits of r4 are clea red. ? the bits of co nt re giste r are set to all "1" except bit 6 (int flag). ? iocb regist er is set to ?1? (disable p60 ~ p67 wake-up functio n ). ? bits 3 and 6 of ioce regi ster a r e cl ea red, and bits 0 , 4, and 5 are set to "1". ? bits 0 and 3 of r3f regi st er an d bits 0 and 3 of iocf regi sters are clea re d. the sl eep (p owe r do wn ) mode i s asse rted by executing the ?sl ep? in stru ctio n. while ente r ing slee p mode, wdt (if enabled ) is clea re d but keep s on runni ng. the controller can b e a w a k en ed by- (1) external res e t input on /reset pin; (2) wd t time-out (if ena ble d ) 1 note: vdd = 5v, set up time perio d = 16.2m s 30% vdd = 3v, set up time perio d = 19.6m s 30% this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 18 em78p 447n otp rom the above two cases will cause the cont rolle r em78p 447 n to reset . the t and p flags of r3 can be use d to determine the source of the re se t (wa k e-up ). in addition to the basi c sle ep1 mode, em78p447n has another sleep mode (designated as sleep2 mode and is invok ed by c l earing t he ioce regis t er ?slpc? bit). in the sleep2 mode, the controller can b e awakened by - (a ) a n y of t he wak e -u p pin s is ?0? a s illust rat ed in figu r e . 5. upon wa king, t he co nt rolle r will co nt inue to execute the succeedi ng a ddress. under this case, before enteri ng sleep2 mode, the wake-up function of the trigger sou r ces (p60 ~p 67 and p74~ p75) sh ould be sele cted (e.g., input pin) and enabl ed (e.g., pull-hi gh, wa ke -up cont rol). it should be noted that af t e r waki ng u p , the wdt is e nable d if the code option bit enwdt is ?0?. the wdt o peration (to be ena bled o r disa bled ) should b e app rop r iately cont rolle d by sof t ware af ter waki ng up. (b) wdt time-out (if enabled) or external reset input on /reset pi n will trigger a cont roller reset. table 4 us a g e of sleep1 and sleep2 mode usage of sle ep1 an d slee p2 mod e s l e e p 2 s l e e p 1 (a) before sleep (a) before sleep 1. set port6 or p74 or p75 i nput 1. execute slep instru cti on 2. enable pull-hi gh and set wdt pre s cal e r over 1:1 (set co nt.7 and cont.3 ~ co nt. 0 ) 3. enable wa ke -up (s et iocb or ioce.0 ) 4. execute seep2 (set ioce.4) (b) after w a k e -u p (b) after w a k e -u p 1. next ins t ruc t ion 1. res e t 2. disa ble wake -u p 3. disa ble wdt (set ioce.5) if port6 input status cha n ged wake-up is use d to wake -u p the em78p44 7s (ca s e [a] abo ve), th e following inst ructions must be ex ecuted before enteri ng sleep2 mode: this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 19 mov a, @1111 111 1b ; set port6 input i o w r 6 mov a, @0xxx1010b ; set port6 pull-hig h , wdt pre s cale r, pre s cale r must set over 1:1 co nt w mov a, @0000 000 0b ; enable port 6 wa ke -up fu nction i o w r b mov a, @xx00xxx1b ; enable sleep2 iow re after wak e - u p n o p mov a, @1111 111 1b ; disabl e port 6 wa ke -up fu nction em78p 447n otp rom i o w r b mov a, @ xx01xxx1b ; disabl e wdt iow re note: after waki ng up from the sleep2 mode, wdt i s au tomatically enabled. the wdt enabled/disabled operation after waking up from sleep2 mode shou ld be appropriat e ly def ined in the software. to avoid rese t from occu rri ng when the port6 status c hang ed inte rrupt enters int o interrupt ve ctor o r is use d to wa ke -up the m cu, the wdt p r e s cale r must b e set above 1 : 1 ratio. table 4 the summar y of the initializ ed values for registers address name reset t y pe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit n a m e c 5 7 c 5 6 c 5 5 c 5 4 c 5 3 c 5 2 c51 c 50 t y p e a b a b a b a b - - - - n / a i o c 5 po w e r - o n 0 1 0 1 0 1 0 1 1 1 1 1 /reset and wdt 0 1 0 1 0 1 0 1 1 1 1 1 w a ke-up from pin chan ge 0 p 0 p 0 p 0 p p p p p bit n a m e c 6 7 c 6 6 c 6 5 c 6 4 c 6 3 c 6 2 c61 c 60 n / a i o c 6 po w e r - o n 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 w a ke-up from pin chan ge p p p p p p p p bit n a m e c 7 7 c 7 6 c 7 5 c 7 4 c 7 3 c 7 2 c71 c 70 n / a i o c 7 po w e r - o n 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 w a ke-up from pin chan ge p p p p p p p p b i t n a m e /phen /in t t s t e p a b p s r 2 psr1 psr0 n / a cont po w e r - o n 1 0 1 1 1 1 1 1 /reset and wdt 1 p 1 1 1 1 1 1 w a ke-up from pin chan ge p p p p p p p p b i t n a m e - - - - - - - - 0 x 0 0 r 0 ( i a r ) po w e r - o n u u u u u u u u /reset and wdt p p p p p p p p w a ke-up from pin chan ge p p p p p p p p b i t n a m e - - - - - - - - 0 x 0 1 r1(t c c ) po w e r - o n 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 w a ke-up from pin chan ge p p p p p p p p b i t n a m e - - - - - - - - 0 x 0 2 r 2 ( p c ) po w e r - o n 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 w a ke-up from pin chan ge * * 0 / p * * 0 / p * * 0 / p * * 0 / p * * 0 / p * * 0 / p **0/p **0/p b i t n a m e g p p s 1 p s 0 t p z dc c this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 20 em78p 447n otp rom 0 x 0 3 r 3 ( s r ) po w e r - o n 0 0 0 1 1 u u u /reset and wdt 0 0 0 t t p p p w a ke-up from pin chan ge p p p t t p p p bit n a m e rsr.1 r sr.0 - - - - - - 0 x 0 4 r 4 ( r s r ) po w e r - o n 0 0 u u u u u u /reset and wdt 0 0 p p p p p p w a ke-up from pin chan ge p p p p p p p p bit name p57 p56 p55 p54 p53 p52 p51 p50 0x05 r5(p5) po w e r-on u u u u u u u u /reset and wdt p p p p p p p p w a ke-up from pin chan ge p p p p p p p p bit n a m e p 6 7 p 6 6 p 6 5 p 6 4 p 6 3 p 6 2 p61 p 60 0 x 0 6 r 6 ( p 6 ) po w e r - o n u u u u u u u u /reset and wdt p p p p p p p p w a ke-up from pin chan ge p p p p p p p p bit n a m e p 7 7 p 7 6 p 7 5 p 7 4 p 7 3 p 7 2 p71 p 70 0 x 0 7 r 7 ( p 7 ) po w e r - o n u u u u u u u u /reset and wdt p p p p p p p p w a ke-up from pin chan ge p p p p p p p p b i t n a m e - - - - ex i f - - t c if 0 x 3 f r 3 f ( i s r ) po w e r - o n u u u u 0 u u 0 /reset and wdt u u u u 0 u u 0 w a ke-up from pin chan ge u u u u p u u p b i t n a m e /wue7 / wue6 /wue5 / wue4 /wue 3 /wue 2 /wue 1 /wue 0 0 x 0 b i o c b po w e r - o n 1 1 1 1 1 1 1 1 /reset and wdt 1 1 1 1 1 1 1 1 w a ke-up from pin chan ge p p p p p p p p b i t n a m e - o d e wdt e s l p c r o c - - /wue 0 x 0 e i o c e po w e r - o n u 0 1 1 0 u u 1 /reset and wdt u 0 1 1 0 u u 1 w a ke-up from pin chan ge u p 1 1 p u u p b i t n a m e - - - - ex i e - - t c ie 0 x 0 f i o c f po w e r - o n u u u u 0 u u 0 /reset and wdt u u u u 0 u u 0 w a ke-up from pin chan ge u u u u p u u p b i t n a m e - - - - - - - - 0 x 0 8 r 8 po w e r - o n 0 0 0 0 0 0 0 0 /reset and wdt 0 0 0 0 0 0 0 0 w a ke-up from pin chan ge p p p p p p p p b i t n a m e - - - - - - - - 0x09~ 0 x 3 e r 9 ~ r 3 e po w e r - o n u u u u u u u u /reset and wdt p p p p p p p p wa ke -u p from pin p p p p p p p p this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 21 em78p 447n otp rom chan ge ** to execute next instru ction after t he ?slpc? bit sta t us of ioce regist e r bei ng on high -to-l o w tran sition. x: not us ed. u: unknown or don?t c a re. p: previous value befo r e reset. t: check t able 5 2. the status of rst, t, and p of status register a reset condition is initi a ted by one of the following events: 1. a power-o n con d ition, 2. a high-low-high pul se on /reset pin, and 3. watch dog timer time-o ut. the value s of t and p (listed in table 5 below) are u s e d to verify the event that trigge red the proce s so r to wake up. table 6 sho w s the events t hat may affect the status of t and p. table 5 the values of rs t, t and p after reset re set type t p powe r on 1 1 /reset during operating mode *p *p /reset wake-up during s l eep1 mode 1 0 /reset wake-up during s l eep2 mode *p *p wdt duri ng ope r ating mo de 0 *p wdt wa ke -u p duri ng sle ep1 mode 0 0 wdt wa ke -u p duri ng sle ep2 mode 0 *p wake-up on pin change during sleep2 mode *p *p *p: previous status b e fore re set table 6 the ev ents tha t ma y affe ct the t and p status event t p powe r on 1 1 wdtc in stru ction 1 1 wd t time-o u t 0 *p slep instru ction 1 0 wake-up on pin ch ange during sleep2 mode *p *p *p: previous value befo r e reset this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 22 em78p 447n otp rom vo ltag e det ect o r p o w er- o n res e t wd te set u p tim e vd d dq cl k cl r cl k reset w d t ti m e o u t wd t /r eset os c ill ato r fig. 8 contr o ller rese t block diagr a m 4.6 interrupt the em78p4 47n h a s two interrupts li ste d belo w : (1) t c c overf l ow inte rru pt (2) external interrupt (/int pin). r3f is the int e rrupt statu s regi ster that reco rd s the interrupt req u e s ts in the relative flags /bits . iocf is the interrupt mask regi ster. the gl obal i n terrupt is e n abled by the eni instructio n and i s disab l ed by the disi instruction. when on e of the interrupts (enabl ed) occurs, the nex t instructi on will be fet c hed from add re ss 0 0 1 h . once in th e interrupt se rvice routin e, the sou r ce of an interrupt can b e dete r mined by polling th e fla g bits i n r3f . the inte rru pt flag bit mu st be cle a re d by instructio ns b e fore lea v ing the interrupt se rvi c e routine a n d before interrupt s are e n a b led to avoid re cursive inte rru pts. the flag (except icif bit) in the interrupt status regi st er (r3f) i s se t regardl ess o f the status of its mask bit or the exe c ution of eni. note that the outcome of r3f are the logic and of r3f an d iocf (refer to fig. 9). t he reti instru ctio n en ds th e int e rrupt routine and ena ble s the gl obal i n te rru pt (the exe c ution of eni). whe n an inte rru pt is gen erated by t he int instru ction (enabl ed ), the nex t instru ctio n will be fetch ed from a d d r e s s 00 2h . this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 23 em78p 447n otp rom in t eni/disi io d rf w r ioc f rd io cf w r ir q n ir q m rf r d io cf / r es et /i rqn vc c rf clk clk q q d p r l c _ p r l c q q _ d fig. 9 interrupt input circuit 4.7 oscillator 1. oscillator modes the em7 8 p4 47n can o p e r ate in th ree d i fferent o sc ill ator m ode s, i . e., high xta l (hxt) oscill ator mode, lo w x t al (lxt ) o s cillato r mod e , and exte rn al rc oscillato r mode (erc) oscillato r mo de. user can sel e ct one of them by program ming ms , hlf and hlp in the code opti on regi ste r . table 7 depi cts ho w these three mode s are de fined. the maximu m limit for operatio nal freq uen cie s of cr y s tal/re so nator unde r differe nt vdds is listed in table 8. table 7 osci llator modes define d b y ms and hlp mode ms hlf hlp erc(external rc o scill ator mode) 0 *x *x hxt(high xtal oscillator mode) 1 1 *x lxt(low xt al oscillator mode) 1 0 0 em78p 447n otp rom table 8 the summar y of maximum opera t ing spe e ds conditions vdd fxt max.(mhz) 2 . 3 4 . 0 3 . 0 8 . 0 two c y c l es with two c l oc ks 5 . 0 2 0 . 0 2. cry s tal oscillator / ce ramic resonators(xtal) em78p44 7n can b e drive n by an extern al clo ck sig n a l throug h the osci pin a s sho w n in fi g. 10 belo w . in most ap plications, pin o s ci and pin osco can be con n e c ted wi th a cry s tal o r ce rami c re so nato r to gene rate o scill ation. fig. 12 de pict s su ch circui t. th e sa me thin g applie s wheth e r it is i n the hxt mode o r in the lxt mode. table 9 prov ides the reco mmend ed val ues of c1 an d c2. since each re son a tor ha s its own attrib ute, user sho u ld refe r to its spe c ification for app ro priat e values of c1 and c2. rs. a serial re sisto r m a y be necessary for at s t rip c u t crys tal or low frequenc y mode. os c i os c o e m 78p 447s e x t. c l o c k fig. 10 cr y s t a l/reso nato r circuit os c i os c o e m 7 8 p 447s c1 c2 xta l rs fig. 1 1 cr y s t a l/re s ona tor circuit this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 25 em78p 447n otp rom table 9 capacitor selection guide for cr y s tal oscillator or ceramic resonator oscillator type freq uen cy m ode freq uen cy c1 (pf ) c2 (pf ) 455 khz 100 ~15 0 100 ~15 0 2.0 mhz 20~40 20~40 ce rami c re sonato r s hxt 4.0 mhz 10~30 10~30 32.768 k h z 2 5 1 5 100k h z 2 5 2 5 lxt 200k h z 2 5 2 5 455k h z 2 0 ~ 4 0 2 0 ~ 1 5 0 1 . 0 m h z 1 5 ~ 3 0 1 5 ~ 3 0 2 . 0 m h z 1 5 1 5 cry s tal oscill ator hxt 4 . 0 m h z 1 5 1 5 3. external rc oscillator mode for some a p p lication s that do not nee d a very prec i s e timing cal c ul a t ion, the rc o scill ator (fig. 15) offers a lot of co st saving s. neve rthele s s, it s hould b e noted that the frequen cy of the rc oscill ator is influen ce d by the sup p ly voltage, the value s of the resi stor (rext), the capa cito r (cext), and even by the op era t ion tempe r at ure. mo re ove r , the fre que ncy al so ch a nge s sli ghtly from on e chi p to anothe r du e to the manufa c turi ng proce ss va riation. in ord e r to m a intain a stabl e system freq u ency, the va lue s o f th e ce xt s h ou ld no t be le ss th an 20p f , and that th e value of rext should not b e gre a ter tha n 1 m ohm. if th ey can not be kept in thi s ra nge, the frequ en cy is easily affe cted by noi se , humidity, and leakage. the small e r the rext in th e rc oscillat o r, the fast er its frequen cy will be. on th e contra ry, fo r very low rext values, for insta n c e, 1 k ? em78p 447n otp rom os c i em 78p 4 47s vc c re x t c ext fig. 12 external rc o sci llator mode circuit table 10 rc oscillator frequencies cex t rex t average f o sc 5v,25 em78p 447n otp rom 1. code option regist er (word 0) wo rd 0 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 - - ec - clks enwdt b t ype hlf osc hlp pr2 pr1 pr0 ? bit 12 em78p 447n otp rom ? bit 4 (osc):oscilla tor type selection. 0:rc type 1:xtal type (xtal1 and x t al2) ? bit 3 (hlp): powe r sel e cti on. 0: low po we r 1: high po we r ? bit 2~0 (pr2~p r0): prot ect bit pr2 ~ pr0 a r e prote c t bits, prote c t type as follo wing pr2 pr1 pr0 protect 0 0 0 e n a b l e 0 0 1 e n a b l e 0 1 0 e n a b l e 0 1 1 e n a b l e 1 0 0 e n a b l e 1 0 1 e n a b l e 1 1 0 e n a b l e 1 1 1 d i s a b l e 2. customer id register (word 1) wo rd 1 bit 12~bit 0 xxxxxxxxx xxxx ? bit 12~0: custom er? s id cod e 4.9 power on consideratio n s any micro c o n t roller i s n o t g uarantee d to start an d o p e r ate p r op erly before the po we r su pply st ays at its steady state. em78p44 7n i s eq uipp ed wi th powe r on voltage dete ctor(povd) with a dete c tin g level is 2.0v. it will work well if vd d rise s fast enoug h (10 m s or less). in many critical appli c ation s , however, extra devices are still requi red to a ssi st in solving power-up probl ems. this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 29 em78p 447n otp rom 4.10 external power on reset circu i t the ci rcuit sh own i n fig.1 6 impleme n ts an external rc to produ ce the re set pul se. th e pul se width (time co nsta n t ) shoul d be kept long eno u gh for vdd to rea c h ed mini mum ope ratio n voltage. this circuit is used when the power supply has slow rise time . be cause the current leakage from the /reset pin is about em78p 447n otp rom 4.11 residue-voltage protection whe n battery is repl ace d , device p o we r (vd d ) is taken off but re sidu e - voltage rem a ins. th e re sidu e-volta ge may trip s belo w vdd mi nimum, but n o t to zero. thi s conditio n m a y cau s e a p oor p o wer on re set. fig.16 and fi g.17 sho w ho w to bu ild the resi due -voltage p r ote c tion ci rcuit. em 78p447n /r eset vd d 40k q1 1n4684 10k 33 k vdd fig. 14 the residu e v o lt age protecti on circuit 1 em 78p447n / r ese t vd d q1 vdd 40k r2 r1 fig. 15 the residu e v o lt age protecti on circuit 2 this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 31 em78p 447n otp rom 4.12 instruction set each inst ru ction in the instru ction set is a 13-bit word divided i n to an op code and on e or more ope ran d s. normally, all in stru ction s a r e execute d wit h in on e si ngl e inst ru ction cycle (o ne in stru ction con s i s ts of 2 oscillato r pe ri ods), unle s s the pro g ra m cou n ter i s ch ange d by in structio n "mo v r2,a", "add r2,a", or by instru cti ons of arithm etic or logi c operation on r2 (e.g. "sub r2,a", "bs(c) r2,6", "clr r2", ??? ? em78p 447n otp rom inst ruc t i on binary hex mnemonic operation st a t us affe ct ed 0 0000 0 001 000 0 001 0 eni enab le interru pt none 0 0000 0 001 000 1 001 1 disi disab le interru pt none 0 0000 0 001 001 0 001 2 ret [t op of stack] ? em78p 447n otp rom inst ruc t i on binary hex mnemonic operation st a t us affe ct ed 1 01kk kkkk kkkk 1kkk jmp k (page, k) em78p 447n otp rom 4.13 timing diagram r e s e t ti m i ng ( c l k = " 0" ) cl k / r es et no p in s t r u c t io n 1 e x ecu t e d td r h t c c i n pu t ti m i ng ( c lk s = " 0 " ) cl k tcc tt c c ti n s a c t e s t i ng : i nput i s dr i v e n a t 2 . 4 v f o r l ogi c " 1 " , a nd 0 . 4 v f o r l ogi c " 0 " . t i m i ng m e a s u r e m e nt s a r e m a d e at 2. 0v f o r l o g i c " 1 " , an d 0. 8v f o r l o g i c " 0 " . a c t est i n put / o ut pu t w a v e f o r m 2. 4 0. 4 2. 0 0. 8 t e st po i n ts 2. 0 0. 8 this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 35 em78p 447n otp rom 5. absolute maximum ratings items rating t e mperature unde r bia s -40 em78p 447n otp rom 6. dc electri cal characteristi cs 6.1 dc electrical characteristic (ta= 25 ? % % em78p 447n otp rom 6.2 ac electrical characteristic (ta=- -40 em78p 447n otp rom 6.3 device characteristic the g r ap hic provid ed in th e followi ng p age s were de rived b a sed o n a limited nu mber of sam p les and are sho w n he re for refe re n c e only. the device cha r a c teri stic illu strated herein a r e not gua ra n t eed for it accu ra cy. in som e gra phi c, the data maybe out of the spe c ified warrante d ope rat i ng ra nge. v i h/v il (i nput pins w ith s c hmitt inv e rter) 0 0.5 1 1.5 2 2 . 533 . 544 . 555 . 5 vdd( vol t ) v i h v il(v o lt) vih m a x(- 4 0 to 85 ) vih ty p 25 vih m i n(- 4 0 to 85 ) vil m a x (-40 to 85 ) vil typ 25 vil m i n (-40 to 85 ) fig. 16 v i h, v il of tcc, /i nt , /reset pin this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 39 em78p 447n otp rom vth (i nput thershold voltag e ) of i / o pins 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.5 3 3.5 4 4.5 5 5.5 vdd(volt) vth(volt) t y p 25 : max ( - 40 : to 85 : ) m i n (- 40 : to 85 : ) fig. 17 vth t h res hold v o lt age o f p60~p6 7, p70~p7 7 vs. vdd this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 40 em78p 447n otp rom v oh/ ioh (v d d = 5 v ) -25 -20 -15 -10 -5 0 01 2 3 45 v oh(v o l t ) ioh(ma) fig.18 port5, port6, and port7 v oh v s . ioh,vdd=5v vo h / io h (vdd=3 v ) -1 0 -8 -6 -4 -2 0 00 . 5 11 . 5 22 . 5 3 vo h ( vo lt) ioh(ma) m i n 85 this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 41 em78p 447n otp rom vo l / i o l ( v dd = 5 v ) 0 10 20 30 40 50 60 70 80 90 01 23 45 6 vo l ( vo l t ) iol(ma) fig. 20 port5, and port6 v o l v s , iol, vdd=5v v o l/i ol (v dd=3v ) 0 5 10 15 20 25 30 35 40 0 0.5 1 1.5 2 2.5 3 vol(volt) iol(ma) m a x - 40 this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 42 em78p 447n otp rom vo l/i o l (5 v) 0 10 20 30 40 50 60 70 80 90 100 012 3456 vol(volt) iol(ma) fig. 22 port7 v o l v s . iol, v d d= 5v vo l/i o l (3 v) 0 5 10 15 20 25 30 35 40 45 0 0.5 1 1.5 2 2.5 3 vol(volt) iol(ma) m a x - 40 this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 43 em78p 447n otp rom w d t time_out 0 5 10 15 20 25 30 35 23 45 6 vdd (volt) wdt period (ms) m a x 85 this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 44 em78p 447n otp rom cext=100pf , ty pical rc o s c f r equency 0 0.2 0.4 0.6 0.8 1 1.2 1.4 2 . 5 3 3 . 5 4 4.5 5 5.5 vdd(vol t ) frequency(m hz) r = 3. 3k r=5.1 k r=10 k r = 100k fig. 25 t y p i cal rc os c frequen c y v s . vdd ce xt= 1 00 p f , t e mp e r at u r e at 25 : e r c o s c fr e q u e n c y v s t e m p.( c e x t =100pf , r e x t =5.1k ) 0.98 0.985 0.99 0.995 1 1.005 - 4 0 - 2 0 0 2 04 06 08 0 t e m p er at u r e( : ) fosc/fosc(25 : ) 3v 5v fig. 26 t y p i cal rc os c frequen c y v s . t e mpera t ur e r an d c are ideal co mponent this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 45 em78p 447n otp rom four conditi ons exis t w i th the oper a ti ng curren t icc1 to icc4. these c ondi tions are a s follo w s ? icc1 ? v d d=3v , fosc = 32 khz, 2clock, wdt disable . icc2 ? v d d=3v , fosc = 32 khz, 2clock, wdt enable. icc3 ? v d d=5v , fosc = 4 mhz, 2clock, wdt en able . icc4 ? v d d=5v , fosc = 10 mhz, 2clock, wdt en able . ty pical i cc1 and i cc2 vs. temperature 9 12 15 18 21 - 4 0 - 2 0 0 2 04 0 6 08 0 tem p erat ure ( : ) current (ua) ty p icc2 ty p icc1 fig. 27 t y p i cal opera t ing curr ent i c c1 and ic c2 v s . t e mperatur e max i mum i cc1 and i cc2 vs. temperature 15 18 21 24 27 - 4 0 - 2 0 0 2 04 0 6 08 0 tem p er at ure ( : ) current (ua) max icc2 max icc1 fig. 28 maximum operating curren t ic c1 and ic c2 v s . t e mperature this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 46 em78p 447n otp rom ty pical i cc3 and i cc4 vs. temperature 0.5 1 1.5 2 2.5 3 3.5 4 - 4 0 - 2 0 0 2 04 06 08 0 tem p er at ure ( : ) current (ma) ty p icc4 ty p icc3 fig. 29 t y p i cal opera t ing curr ent i c c3 and ic c4 v s . t e mperatur e maxim u m icc3 and icc4 vs. tem p erature ? ? ? ? ? ? ? ? ?? ?? ? ? ? ? ? ? ? ? t e mper atur e ( : ) current (ma) max icc4 max icc3 fig. 30 maximum operating curren t ic c3 and ic c4 v s . t e mperature this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 47 em78p 447n otp rom t w o con d itio ns exist w i th the st an db y curren t isb1 and isb2. th ese con d itio ns are as follo w ? isb1 ? vdd=5v , wdt dis a ble isb2 ? vdd=5v , wdt en able ty pical i s b 1 and i s b 2 vs. temperature 0 3 6 9 12 - 4 0 - 2 0 0 2 04 0 6 08 0 tem p erat ure ( : ) current (ua) typ isb2 typ isb1 fig. 31 t y p i cal s t andb y curren t isb1 and isb2 v s . t e mperature max i mum i s b 1 and i s b 2 vs. temperature 0 3 6 9 12 15 - 4 0 - 2 0 0 2 04 0 6 08 0 tem p erat ure ( : ) current (ua) max i sb2 max i sb1 fig. 32 maximum s t andby current i s b1 and isb2 v s . t e mperature this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 48 em78p 447n otp rom ope r a ting volta g e ( - 4 0 : ~85 : ) 0 5 10 15 20 25 2 2.5 3 3.5 4 4.5 5 5 .5 6 vdd (volt) frequency (m hz) fig. 33 oper ating v o lt ag e in t e mpera t ure rang e from -40 : to 85 : this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 49 em78p 447n otp rom em78p447n hxt i - v 0 0.5 1 1.5 2 2.5 3 0123 456 volt(v) i(ma) max min fig. 34 em78p447 n i-v curv e operating at 4 mhz em78p447n l x t i - v 0 5 10 15 20 25 30 35 40 01 23 45 6 volt(v) i(ua) max min fig. 35 em78p447 n i-v curv e operating at 32.7 68 khz this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 50 em78p 447n otp rom appendix package ty pes: otp mcu packag e type pin count packag e size em78p44 7 n a p d i p 2 8 6 0 0 m i l em78p44 7 n a m s o p 2 8 3 0 0 m i l em78p44 7 n a s s s o p 2 8 2 0 9 m i l em78p44 7 n b p d i p 3 2 6 0 0 m i l em78p44 7 n b w m s o p 3 2 4 5 0 m i l this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 51 em78p 447n otp rom package information 28-l ead plas tic dual inline p ackag e em78p 447n otp rom 32-l ead plas tic dual inline p ackag e em78p 447n otp rom 28-l ead plas tic small outline p ackag e em78p 447n otp rom 32-l ead plas tic small outline p ackag e em78p 447n otp rom 28-l ead shri nk small outline package em78p 447n otp rom elan ( h ea d q uarte r ) m i croelect r o nics c o r p . , ltd. addres s : no. 1 2 , innov a t i on 1 s t. rd. sc ien c e- ba sed in du stri al p a rk , hs i n ch u ci ty , ta i w an. te le phone : 88 6- 3- 5639977 f a cs imi l e : 886- 3- 5639966 elan ( h .k .) microele ct ronics cor p ., ltd. addre s s : r m . 1005b, 10/ f , em pi r e cent re, 68 mody r o ad, ts im shats u i , kowl oon, hong kong. te le phone : 85 2- 27233376 f a cs imi l e : 852- 27237780 e-mail : ela n h k @emc.co m .h k elan mi cro e lectronics shenzhen, ltd. address : ss m e c bldg . 3f , g a oxin s . ave. 1st , so uth are a , sh enzh en high -t ech indu stri al p a rk., sh enzh en te le phone : 86 - 755- 2601056 5 f a cs imi l e : 86-755- 260105 00 elan mi cro e lectronic s s h ang h ai, ltd. addre s s : #23 buil d i ng n o . 1 1 5 lane 572 bibo r o ad. zhang j i a ng , hi- t e c h park, shanghai te le phone : 86 - 21- 50803866 f a cs imi l e : 86-21- 5080460 0 e l a n i n fo r m at i o n t e c h no l o g y g r o u p . addre s s : 1821 sarat o ga avenue, suit e 250, sarat o ga, c a 95070, u sa te le phone : 1 - 408- 366- 8225 f a cs imi l e : 1- 4 08- 366- 8220 elan mi cro e le ctron i cs c o rp . (eur op e) addre s s : d u b e ndorfs t r as se 4, 8051 zuri c h , swi t ze rl and te le phone : 41 - 43- 2994060 f a cs imi l e : 41-43- 2994079 ema il : inf o @e l a n- eur o pe .co m web-s i t e : w w w.elan -europ e.com copy right ? 2 004 elan mi croele c tro n ics co rp. all rig h ts re se rved. elan own s the intellect ual prope rty righ ts, concept s, idea s, inventions, kno w -ho w (whethe r p a tentable or not) relat ed to the information a n d tech nolo g y (herei n after refe rred as " informa t ion and technol ogy") mention ed a b o ve, and all it s related i ndu st rial pro p e r ty right s thro ug hout the wo rl d, as n o w may exist or to be cre a ted in the future. elan rep r e s ents no wa rra n ty for the us e of the speci f ication s describe d , either expressed or impli e d, includi ng, but not limited, to the implied warranties of mercha ntabili ty and fitness for particular purpo se s. th e entire ri sk a s to the qualit y and perfo rman ce of the applicatio n is with the use r . in no even shall el an be liable for any loss or dama ge to revenue s, profits or g o o d will or othe r spe c ial, inci d ental, i ndire ct and con s e q u ential dama g e s of any kind , resulting from the p e rf orma nce or f a ilure to pe rform, in cludi n g witho u t limitation any int e rruption of busi n e ss, whateve r resulting from b r each of co ntract or b r e a ch of warranty, e v en if elan has be en a d vised of the possibility of such damages. the spe c ifications of the produ ct and its applie d techn o logy will be update d o r ch ange d time b y time. a ll the inform atio n and expl an ations of the produ cts i n th is web s ite is only for your referen c e. t he a c tual spe c ification s and appli ed tech nolo g y wil l be based on each confi r m ed order. elan re se rves the rig h t to modify th e informati o n without prio r notificati on. the most u p -to-day informatio n is available on the web s ite h ttp://www.em c.co m.tw . this specification is subject to cha nge w i thout prio r notice. 10.21.2004 (v1.0 ) 57 |
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